View MDT11P0122_4669071.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MDT11P0122
1General Description
This EPROM-Based 8-bit micro-controller uses a fully static CMOS technology process to achieve higher speed and smaller size with the low power consumption and high noise immunity. On chip memory includes 4K words of EPROM, and 176 bytes of static RAM. The application areas of this MDT11P0122 range from appliance motor control and high speed automotive to low power remote transmitters/receivers and telecommunications processors, such as Remote controller, small instruments, toy, automobile and keyboard ... etc.
2Features
RISC CPU Fully static design 37 single word instructions 4K x 14 program memory. 176 bytes RAM for data 25 bi-directional I/O Eight level hardware stacks Watchdog timer with on-chip RC oscillator. Interrupt capability Timer0 : 8-bit timer with 8-bit prescaler Timer1 : 16-bit timer 16-bit Timer1 compare register. Sleep mode for power saving. PB with port change wake-up interrupt. LCD29 Segments,4 commons.(27 x 4 at LQFP Package) 1/2,1/3,1/4 multiplex at 1/3,1/2 bias. 2 channel comparator
3. Applications
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.1 2007/11 VER 1.0
MDT11P0122
4. IC Diagram
(1)Pin Diagram
PA2/CMPP1I
PA3/CMP1R
PA1/CMP0R
PA0/CMP0I
PD7/COM1
PD6/COM2
/MCLR
COM0
VDD
64 63 62 61 60 59 PA4/RTCC PA5 PB1 PB0/IRQ PC3 PC4 PC5 C1 C2 1 2 3 4 5 6 7 8 9
VSS
MDT11P0122LQ11
PB2
PB3
58 57 56 55 54 53 52 51 50 49 48 PD5/COM3 47 PG6/SEG26 46 PG5/SEG25 45 PG4/SEG24 44 PG3/SEG23 43 PG2/SEG22 42 PG1/SEG21 41 PG0/SEG20 40 PF7/SEG19 39 PF6/SEG18 38 PF5/SEG17 37 PF4/SEG16 36 PF3/SEG15 35 PF2/SEG14 34 PF1/SEG13 33 PF0/SEG12
PB4
PB5
PB7
PB6
Vlcd 2 10 Vlcd 3 11 VDD 12 VSS 13 OSCI 14 OSCO 15 PC0/T1OSCO 16 17 18 19 20 21 22 PC1/T1OSCI PC2 NC VLCD PD1/SEG1 PD0/SEG0 23 24 25 26 27 28 29 30 31 32 PD2/SEG2 PD3/SEG3 PD4/SEG4 PE0/SEG5 PE1/SEG6 PE2/SEG7 PE3/SEG8 PE4/SEG9 PE5/SEG10 PE6/SEG11
Device MDT11P0122LQ11 MDT11P0122
LCD dot 4 X 27 4 X 29
Package 64 PIN LQFP COB
Remark
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.2 2007/11 VER 1.0
MDT11P0122
(2)pad diagram
IC substrate connect to VSS VDD (pad 14,55), VSS (pad 15, 65) must to be connect
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.3 2007/11 VER 1.0
MDT11P0122
(3)pad Coordinates PAD-No
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
PAD Name
PA2 PA3 PA4 PA5 PB1 PB0 PC3 PC4 PC5 C1 C2 VLCD2 VLCD3 VDD VSS OSC1 OSC2 PC0 PC1 PC2 VLCD PD0 PD1 PD2 PD3 PD4 PE7 PE0 PE1 PE2 PE3 PE4 PE5
X
68.00 68.00 68.00 68.00 68.00 68.00 68.00 68.00 68.00 68.00 68.00 68.00 68.00 68.00 68.00 68.00 68.00 68.00 68.00 68.00 68.00 73.00 173.00 273.00 373.00 473.00 573.00 673.00 773.00 873.00 973.00 1073.00 1173.00
Y
2278.00 2178.00 2078.00 1978.00 1878.00 1778.00 1678.00 1578.00 1478.00 1378.00 1278.00 1178.00 1078.00 978.00 878.00 778.00 678.00 578.00 478.00 378.00 278.00 68.00 68.00 68.00 68.00 68.00 68.00 68.00 68.00 68.00 68.00 68.00 68.00
PAD-No PAD Name
34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 PE6 PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 PG7 PG0 PG1 PG2 PG3 PG4 PG5 PG6 PD5 PD6 PD7 COM0 VDD PB6 PB7 PB5 PB4 MCLRB PB3 PB2 PA0 PA1 VSS
X
1468.00 1468.00 1468.00 1468.00 1468.00 1468.00 1468.00 1468.00 1468.00 1468.00 1468.00 1468.00 1468.00 1468.00 1468.00 1468.00 1468.00 1468.00 1468.00 1468.00 1468.00 1357.80 1257.80 1157.80 1057.80 957.80 831.80 724.90 624.90 524.90 424.90 324.90
Y
77.00 177.00 277.00 377.00 477.00 577.00 677.00 777.00 877.00 977.00 1077.00 1177.00 1277.00 1377.00 1477.00 1577.00 1677.00 1777.00 1877.00 1977.00 2077.00 2318.00 2318.00 2318.00 2318.00 2318.00 2318.00 2318.00 2318.00 2318.00 2318.00 2318.00
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.4 2007/11 VER 1.0
MDT11P0122
5. Pin function description
Pin name
OSC1 OSC2 /MCLR
Type Buffer type
I O I ST Oscillator input Oscillator out
Description
PA0/CMP0I PA1/CMP0R PA2/CMP1I PA3/CMP1R PA4/RTCC PA5
I/O I/O I/O I/O I/O I/O
TTL TTL TTL TTL ST TTL
Reset input Bi-directional I/O port A. Port A can be software programmed for internal 50K ohm pull-up PA0 ~PA3 can use TTL level I/O or Comaparator input. Output_Lo sink current only 14mA
Can be clock input to Timer0.
Bi-directional I/O port B. Port B can be software programmed for internal 50K ohm pull-up on all pins. PB0-PB7 can generate interrupt on pin state change. PB0/IRQ can be the external interrupt pin. PB0/IRQ PB1 PB2 PB3 PB4 PB5 PB6 PB7 I/O I/O I/O I/O I/O I/O I/O I/O ST/TTL TTL TTL TTL TTL TTL TTL TTL Bi-directional I/O port C. Port C can be software programmed for internal 100K pull-up on all pins. PC0 can be Timer1 oscillator output or Timer1 clock input. PC1 can be Timer1 oscillator input. PC1 PC2 PC3 PC4 PC5 PD0/SEG00 PD1/SEG01 PD2/SEG02 PD3/SEG03 PD4/SEG04 I/O I/O I/O I/O I/O I/O/L I/O/L I/O/L I/O/L I/O/L ST ST ST ST ST ST ST ST ST ST Bi-directional I/O/LCD Driver port. PD0~PD4 are open drain I/O or LCD Segment driver PC2 can be Timer1 compare output.
PC0
I/O
ST
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.5 2007/11 VER 1.0
MDT11P0122
Pin name PD5/COM3 PD6/COM2 PD7/COM1 PE0/SEG05 PE1/SEG06 PE2/SEG07 PE3/SEG08 PE4/SEG09 PE5/SEG10 PE6/SEG11 PE7/SEG27 PF0/SEG12 PF1/SEG13 PF2/SEG14 PF3/SEG15 PF4/SEG16 PF5/SEG17 PF6/SEG18 PF7/SEG19 PG0/SEG20 PG1/SEG21 PG2/SEG22 PG3/SEG23 PG4/SEG24 PG5/SEG25 PG6/SEG26 PG7/SEG28 COM0 C1 C2 VLCD VLCD2 VLCD3 VDD Vss Type I/L I/L I/L I/L I/L I/L I/L I/L I/L I/L I/L I/L I/L I/L I/L I/L I/L I/L I/L I/L I/L I/L I/L I/L I/L I/L I/L L Buffer type ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST LCD Common 0 LCD voltage charge pump pin 1 LCD voltage charge pump pin 2 LCD voltage input pin LCD voltage pin(1/2VDD) LCD voltage pin (3/2VDD) Power input Ground pin Digital input or LCD Segment Driver port Digital input or LCD Segment Driver port Digital input or LCD Segment Driver port Description PD5~PD7 are digital input or LCD Common driver
**note : I:input
O:output
L:lcd
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.6 2007/11 VER 1.0
MDT11P0122
6. Memory Mapping
6.1 Program memory : 0000h Reset Vector 0001h 0002h 0003h 0004h Peripheral interrupt Vector 0005h Program memory (Page 0) 07FFh 0800h Program memory (Page 1) 0FFFh
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.7 2007/11 VER 1.0
MDT11P0122
6.2 Register file map BANK 0 I. ADDR 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 70h 7Fh RTCC PCL STATUS MSR Port A Port B Port C Port D Port E PCHLAT INTS PIFB1 TMR1L TMR1H T1STA BANK 1 I. ADDR TMR PCL STATUS MSR COIO A COIO B COIO C COIO D COIO E PCHLAT INTS PIEB1 PSTA CMPPH BANK 2 I. ADDR RTCC PCL STATUS MSR Port B Port F Port G PCHLAT INTS LCDPFS LCDFS LCDCTL LCD00 LCD01 LCD02 LCD03 LCD04 LCD05 LCD06 LCD07 LCD08 LCD09 LCD10 LCD11 LCD12 LCD13 LCD14 LCD15 BANK 3 I. ADDR TMR PCL STATUS MSR COIO B COIO F COIO G PCHLAT INTS
80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h F0h FFh
100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh 120h 17Fh 17Fh
180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h 1F0h 1FFh
CCP1L CCP1H CCPCTL
General Purpose Register
General Purpose Register Access 70h~7Fh
Access 70h~7Fh
Access 70h~7Fh
Unimplemented memory location.
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.8 2007/11 VER 1.0
MDT11P0122
BANK 1
R00 R01 IAR(Indirect addressing register) RTCC (Real Time Counter/Counter Register) Timer0 register PCL (Program Counter Low Byte) Low order 8 bits of the Program Counter (PC) STATUS (Status register) Bit Symbol 0 C 1 HC 2 Z 3 /PF 4 TO 5 RBS0
R02
R03
6
RBS1
Function Carry bit Half Carry bit Zero bit Power loss Flag bit WDT TIME OUT bit Register page select bit 0 0 00/H --- 7F/H 0 1 80/H --- FF/H 1 0100/H --- 17F/H 1 1180/H --- 1FF/H Register page select bit 0 00/H--- FF/H 1100/H---1FF/H
7
RBS2
R04H : MSR (Memory Select Register) Indirect data memory address pointer. R05H : Port A PortA
PA7 PA6 PA5 PA0~PA5portA I/O register. PA6~PA7always read as 0.
PA4
PA3 PA2 Always available
PA1
PA0
R06H : Port B PortB PB7
PB4 PB3 Always available PB0~PB7Have pin change interrupt
PB6
PB5
PB2
PB1
PB0
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.9 2007/11 VER 1.0
MDT11P0122
R07H : Port C PortC PC7 PC6 PC5 PC4 PC0~PC5portA I/O register. PC6~PC7always read as 0. R08H : Port D PortD PD7
PC3 PC2 Always available
PC1
PC0
PD6
PD5
PD4 PD3 Always available
PD2
PD1
PD0
R09H : Port E PortE PE7
PE6
PE5
PE4 PE3 Always available
PE2
PE1
PE0
R0AH : PCHLAT(Program counter high byte.) BIT 7~0 PCH4 Bit0~4Hiht byte of PC. Bit5~7always read as 0
PCH3
PCH2
PCH1
PCH0
R0BH : INTS(Interrupt control register.) Bit Symbol Function 0 RBIF PORT B change interrupt flag. 1 INTF PB0/IRQ external interrupt flag bit. 2 TIF Timer0 overflow interrupt flag bit. 0 disable PB change interrupt 3 RBIE 1 enable PB change interrupt 0 disable INT interrupt 4 INTS 1 enable INT interrupt 0 disable TMR0 interrupt 5 TIS 1 enable TMR0 interrupt 0 disable all peripheral interrupt 6 PEIE 1 enable all peripheral interrupt 0 disable global interrupt 7 GIS 1 enable global interrupt R0CH : PIFB1(Peripheral interrupt flag register.) BIT 7~0 LCDIF Bit 0Timer1 overflow interrupt flag bit Bit 7LCD interrupt flag bit Bit1~6always read as 0
-
-
-
TMR1IF
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.10 2007/11 VER 1.0
MDT11P0122
R0EH : TMR1L(Timer1 data register low byte.) ROFH : TMR1H(Timer1 data register high byte.) R10H : T1STA(Timer1 control register) Bit Symbol Function 0 Stop TMR1 0 TMR1ON 1 Enable TMR1 0 Internal clock (Fosc/4) 1 TMR1CLK 1 External clock from pin PC0 TMR1CLK = 1 0 Synchronize external clock ______ 1 Do not synchronize external clock 2 T1SYNC TMR1CLK = 0 This bit is ignored 0 TMR1 Oscillator is shut off 3 T1OSCEN 1 TMR1 Oscillator is enable 1 1 = 18 Prescale value T1CKPS1 1 0 = 14 Prescale value ~ 4~5 0 1 = 12 Prescale value T1CKPS0 0 0 = 11 Prescale value 6~7 Unimplemented
R15H : CCP1L(Timer1 compare LSB) R16H : CCP1H(Timer1 compare MSB) R17H : CCPCTL Bit Symbol 0 1~7 CCPM0 0 COMPARE off 1 COMPARE on
Function
Unimplemented.
R20H~R7FH : General purpose register
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.11 2007/11 VER 1.0
MDT11P0122
BANK 1
R81H : TMR(Time Mode Register) Bit Symbol Function Prescaler Value RTCC rate WDT rate 12 11 000 001 14 12 010 18 14 011 1 16 18 0~2 PS0~2 100 1 32 1 16 101 1 64 1 32 101 1 128 1 64 111 1 256 1 128 Prescaler assignment bit 0 RTCC 3 PSC 1 Watchdog Timer RTCC signal edge 0 Increment on low-to-high transition on RTCC pin 4 TCE 1 Increment on high-to-low transition on RTCC pin RTCC signal set 0 Internal instruction cycle clock 5 TCS 1 Transition on RTCC pin Interrupt edge select 0 Interrupt on falling edge on PB0 6 IES 1 Interrupt on rising edge on PB0 PORTB pull-hi 0 PORTB pull-hi are enable 7 /PBPH 1 PORTB pull-hi are disable R85H : CPIO A (Control Port I/O Mode Register) 0 I/O pin in output mode; 1 I/O pin in input mode. R86H : CPIO B (Control Port I/O Mode Register) 0 I/O pin in output mode; 1 I/O pin in input mode. R87H : CPIO C (Control Port I/O Mode Register) 0 I/O pin in output mode; 1 I/O pin in input mode.
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.12 2007/11 VER 1.0
MDT11P0122
R88H : CPIO D (Control Port I/O Mode Register) 0 I/O pin in output mode; 1 I/O pin in input mode. R89H : CPIO E (Control Port I/O Mode Register) 0 I/O pin in output mode; 1 I/O pin in input mode. R8CH : PIEB1 Bit 0 1~6 7
Symbol TMR1IE LCDIE
Function TMR1 interrupt enable bit 0 disable TMR1 interrupt 1 enable TMR1 interrupt Unimplemented. LCD interrupt enable bit 0 : disable LCD interrupt 1 : enable LCD interrupt
R8EH : PSTA Bit 0 1 2~7 R90H:CMPPH Bit 0 1
Symbol PORB Unimplemented.
Function 0:Power on Reset occurred 1:No Power on Reset occurred Unimplemented.
2~3
4 5 6~7
Function 0:PA0,PA1 as TTL input CMPS0 1:PA0,PA1 as Comparaotr input 0:PA2,PA3 as TTL input CMPS1 1:PA2,PA3 as Comparaotr input 1 1 = PA1,PA3 select extrenal vrefence voltage 1 0 = PA1,PA3 select 3/4 VDD as vrefence voltage CMPRS0~1 0 1 = PA1,PA3 select 1/2 VDD as vrefence voltage 0 0 = PA1,PA3 select 1/4 VDD as vrefence voltage 0:Port A pull up enable PAHR 1:Port A pull up disable 0:Port C pull up enable PCHR 1:Port C pull up disable -
Symbol
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.13 2007/11 VER 1.0
MDT11P0122
BANK2
R107H : PortF PortF PF7 PF6 PF5 PF4 PF3 PF2 Always read available PF1 PF0
108H : PortG PortG PG7 PG6 PG5 PG4 PG3 PG2 Always read available PG1 PG0
R10DH LCDPFS(Lcd pin function select) Bit 0 1 2 3 4 5 6 7 Symbol DL00 DL05 DL09 DL12 DL16 DL20 DL27 DL29 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function PD0~PD4 as digital input PD0~PD4 as LCD driver PE0~PE3 as digital input PE0~PE3 as LCD driver PE4~PE6 as digital input PE4~PE6 as LCD driver PF0~PF3 as digital input PF0~PF3 as LCD driver PF4~PF7 as digital input PF4~PF7 as LCD driver PG0~PG6 as digital input PG0~PG6 as LCD driver PG7,PE7 as digital input PG7,PE7 as LCD driver PD5~PD7 as digital input PD5,PD7 as LCD driver
R10EH : LCDFS(LCD frame frequency select) BIT 7~0 FS3 FS2 FS1 FS0
Common select 1/2 1/3 1/4
Frame frequency Clock/[128 * (FS3:FS0+1)] Clock/[ 96 * (FS3:FS0+1)] Clock/[128 * (FS3:FS0+1)]
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.14 2007/11 VER 1.0
MDT11P0122
R10FH : LCDCTL(LCD control) Bit Symbol Function LCD Common select bits 0 0 -0~1 LCDS0~1 0 1 1/2 (use COM 0,1) 1 0 1/3 (use COM 0,1,2) 1 1 1/4 (use COM 0,1,2,3) Clock select 0 0 sysclk/256 2~3 CLKS0~1 0 1 Timer1 clk (must enable T1 osc) 1 X internal RC Cap mode and Resistor mode select 0 Resistor mode 4 CRS 1 Cap mode BIAS Select 0 Use 1/2 bias mode 5 BIASS 1 Use 1/3 bias mode LCD enabled in Sleep mode 0 LCD enable in sleep mode 6 SLPE 1 LCD disable in sleep mode LCD enable bit 0 LCD disable 7 LCDE 1 LCD enable
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.15 2007/11 VER 1.0
MDT11P0122
R110H~R11FH : LCD00~LCD15(LCD data register 00~15) Address Symbol
R110H R111H R112H R113H R114H R115H R116H R117H R118H R119H R11AH R11BH R11CH R11DH R11EH R11FH LCD00 LCD01 LCD02 LCD03 LCD04 LCD05 LCD06 LCD07 LCD08 LCD09 LCD10 LCD11 LCD12 LCD13 LCD14 LCD15
BIT7
SEG07 COM0 SEG15 COM0 SEG23 COM0 *SEG31 COM0 SEG07 COM1 SEG15 COM1 SEG23 COM1 *SEG31 COM1 SEG07 COM2 SEG15 COM2 SEG23 COM2 *SEG31 COM2 SEG07 COM3 SEG15 COM3 SEG23 COM3 *SEG31 COM3
BIT6
SEG06 COM0 SEG14 COM0 SEG22 COM0 *SEG30 COM0 SEG06 COM1 SEG14 COM1 SEG22 COM1 *SEG30 COM1 SEG06 COM2 SEG14 COM2 SEG22 COM2 *SEG30 COM2 SEG06 COM3 SEG14 COM3 SEG22 COM3 *SEG30 COM3
BIT5
SEG05 COM0 SEG13 COM0 SEG21 COM0 *SEG29 COM0 SEG05 COM1 SEG13 COM1 SEG21 COM1 *SEG29 COM1 SEG05 COM2 SEG13 COM2 SEG21 COM2 *SEG29 COM2 SEG05 COM3 SEG13 COM3 SEG21 COM3 *SEG29 COM3
BIT4
SEG04 COM0 SEG12 COM0 SEG20 COM0 SEG28 COM0 SEG04 COM1 SEG12 COM1 SEG20 COM1 SEG28 COM1 SEG04 COM2 SEG12 COM2 SEG20 COM2 SEG28 COM2 SEG04 COM3 SEG12 COM3 SEG20 COM3 SEG28 COM3
BIT3
SEG03 COM0 SEG11 COM0 SEG19 COM0 SEG27 COM0 SEG03 COM1 SEG11 COM1 SEG19 COM1 SEG27 COM1 SEG03 COM2 SEG11 COM2 SEG19 COM2 SEG27 COM2 SEG03 COM3 SEG11 COM3 SEG19 COM3 SEG27 COM3
BIT2
SEG02 COM0 SEG10 COM0 SEG18 COM0 SEG26 COM0 SEG02 COM1 SEG10 COM1 SEG18 COM1 SEG26 COM1 SEG02 COM2 SEG10 COM2 SEG18 COM2 SEG26 COM2 SEG02 COM3 SEG10 COM3 SEG18 COM3 SEG26 COM3
BIT1
SEG01 COM0 SEG09 COM0 SEG17 COM0 SEG25 COM0 SEG01 COM1 SEG09 COM1 SEG17 COM1 SEG25 COM1 SEG01 COM2 SEG09 COM2 SEG17 COM2 SEG25 COM2 SEG01 COM3 SEG09 COM3 SEG17 COM3 SEG25 COM3
BIT0
SEG00 COM0 SEG08 COM0 SEG16 COM0 SEG24 COM0 SEG00 COM1 SEG08 COM1 SEG16 COM1 SEG24 COM1 SEG00 COM2 SEG08 COM2 SEG16 COM2 SEG24 COM2 SEG00 COM3 SEG08 COM3 SEG16 COM3 SEG24 COM3
* These bits don't BANK3
R187H : CPIO F R188H : CPIO G
display, but can used as general ram.
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.16 2007/11 VER 1.0
MDT11P0122
7.Reset Condition for all Registers
Register IAR RTCC PCL STATUS MSR PORT A PORT B PORT C PORT D PORT E PCHLAT INS PIFB1 TMR1L TMR1H T1STA CCPR1L CCPR1H CCPCTL MTR CPIOA CPIOB CPIOC CPIOD CPIOE PIEB1 PWRCON CMPPH PORT F PORT G Power-On Reset, Power range Address /MCLR or WDT Reset detector Reset 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Eh 0Fh 10h 15h 16h 17h 81h 85h 86h 87h 88h 89h 8Ch 8Eh 90h 107h 108h
N/A N/A
Wake-up from SLEEP
N/A
xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx --00 0000 xxxx xxxx --xx xxxx 0000 0000 0000 0000 ---- 0000 0000 000x ---- ---x xxxx xxxx xxxx xxxx --00 0000 xxxx xxxx xxxx xxxx --1- ---0 1111 1111 --11 1111 1111 1111 --11 1111 1111 1111 1111 1111 ---- ---0 ---- --#0011 0000 0000 0000 0000 0000
uuuu uuuu 0000 0000 000# #uuu uuuu uuuu --00 0000 uuuu uuuu --uu uuuu 0000 0000 uuuu uuuu ---- 0000 0000 000u ---- ---u uuu uuuu uuu uuuu --00 0000 uuuu uuuu uuuu uuuu --1- ---0 1111 1111 --11 1111 1111 1111 --11 1111 1111 1111 1111 1111 ---- ---0 ---- --u0011 uuuu 0000 0000 0000 0000
uuuu uuuu
PC+1
000# #uuu uuuu uuuu --uu uuuu uuuu uuuu --uu uuuu uuuu uuuu uuuu uuuu ---- uuuu uuuu uuuu ---- ---u uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu uuuu uuuu --u- ---u uuuu uuuu --uu uuuu uuuu uuuu --uu uuuu uuuu uuuu uuuu uuuu ---- ---u ---- --u00uu uuuu uuuu uuuu uuuu uuuu
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.17 2007/11
VER 1.0
MDT11P0122
Register LCDPFS LCDFS LCDCTL Lcd00~15 CPIO F CPIO G Power-On Reset, Power range Address /MCLR or WDT Reset detector Reset 10Dh 10Eh 10Fh 110h 186h 187h 1111 1111 ---- 0000 0000 0000 xxxx xxxx 1111 1111 1111 1111 1111 1111 ---- 0000 0000 0000 uuuu uuuu 1111 1111 1111 1111 Wake-up from SLEEP uuuu uuuu ---- uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
Note uunchanged xunknown - unimplemented read as "0" #value depends on the condition of the following table Condition POWR ON RESET /MCLR reset (not during SLEEP) /MCLR reset during SLEEP WDT reset (not during SLEEP) WDT reset during SLEEP Interrupt Wake-up during SLEEP Status bit 4 1 u 1 0 0 1 Status bit 3 1 u 0 1 0 0 PWRCON bit 1 0 u u u u u
8. Instruction Set
Instruction Code Mnemonic Operands Function No operation Clear Watchdog timer Sleep mode Load W to TMR register Control I/O port register Store W to register Load register Load immediate to W Increment register R R, t I R, t R Operation None 0WT 0WT, stop OSC WTMR WCPIO WR Rt IW [R(0~3) (4~7)]t R + 1t W + Rt R Wt (R+/W+1t) r TF, PF TF, PF None None None Z None None Z None C, HC, Z C, HC, Z Status
010000 00000000 NOP 010000 00000001 CLRWT 010000 00000010 SLEEP 010000 00000011 TMODE 010000 00000rrr 010001 1rrrrrrr 011000 trrrrrrr 111010 iiiiiiii 010111 trrrrrrr 011001 trrrrrrr 011010 trrrrrrr 011011 trrrrrrr 011100 trrrrrrr CPIO STWR LDR LDWI INCR
SWAPR R, t Swap halves register
INCRSZ R, t Increment register, skip if zero R + 1t ADDWR R, t Add W and register SUBWR R, t Subtract W from register
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.18 2007/11
VER 1.0
MDT11P0122
Instruction Code 011101 trrrrrrr 011110 trrrrrrr 010010 trrrrrrr 110100 iiiiiiii 010011 trrrrrrr 110101 iiiiiiii 010100 trrrrrrr 110110 iiiiiiii 011111 trrrrrrr 010110 trrrrrrr 010101 trrrrrrr 010000 1xxxxxxx 010001 0rrrrrrr 0000bb brrrrrrr 0010bb brrrrrrr 0001bb brrrrrrr 0011bb brrrrrrr Mnemonic Operands DECR Function Operation R 1t R Wt i WW R Wt i WW R Wt i WW /Rt R(n) R(n-1), CR(7), R(0)C RLR CLRW CLRR BCR BSR BTSC BTSS R R, b R, b R, b R, t Rotate left register Clear working register Clear register Bit clear Bit set Bit Test, skip if set Long CALL subroutine Long JUMP to address Add immediate to W Subtract W from immediate Return from interrupt Return from subroutine R(n)r(n+1), CR(0), R(7)C 0W 0R 0R(b) 1R(b) Skip if R(b)=0 Skip if R(b)=1 nPC, PC+1Stack 101nnn nnnnnnnn LJUMP n 110001 iiiiiiii 110111 iiiiiiii 111000 iiiiiiii RTIW i ADDWI SUBWI nPC None None C,HC,Z C,HC,Z None None Return, place immediate to W StackPC, iW PC+1PC, W+iW i-WW StackPC,1GIS StackPC 010000 00001001 RTFI 010000 00000100 RET Z Z None None None None None C Status Z None Z Z Z Z Z Z Z C
R, t Decrement register
DECRSZ R, t Decrement register, skip if zero R 1t ANDWR R, t AND W and register ANDWI IORWI XORWI COMR RRR i i R, t i AND W and immediate Inclu. OR W and register Inclu. OR W and immediate Exclu. OR W and immediate Rotate right register IORWR R, t
XORWR R, t Exclu. OR W and register R, t Complement register
R, b Bit Test, skip if clear
100nnn nnnnnnnn LCALL n
Note : W WT TMODE CPIO TF PF
: : : : : :
Working register Watchdog timer TMODE mode register Control I/O port register ( PA, PB, PC Only ) Timer overflow flag Power loss flag
b t
: : 0 1 R: C: HC :
Bit position Target : Working register : General register General register address Carry flag Half carry VER 1.0
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.19 2007/11
MDT11P0122
PC OSC Inclu. Exclu. AND : : : : : Program Counter Oscillator Inclusive `' Exclusive `' Logic AND `' Z / x i n : : : : : Zero flag Complement Don't care Immediate data ( 8 bits ) Immediate address
9. Electrical Characteristics
(Operating temperature at 25).
Sym
Description
Condition
Min 2.5
Typ
Max 6.3 1.0
Unit V V
VDD Operating voltage VIL VIH IIL VOL VOH Input Low Voltage Input high Voltage PA, PB VDD=5V VDD=5V
-0.6
2.0 3.2
VDD VDD +/-1 0.4 0.1 3.3 4.5 50k 50K 100K 0.1 2 5 10 18 35 15 5.5 20 7 1.0
V V A V V V V A A A A A A A
PC, PD, PE, PF, PG RTCC, /MCLR VDD=5V Input leakage current Output Low Voltage PA, PB, PC, PD Output High Voltage PA, PB, PC PortA pullhigh resister Rph PortB pullhigh resister PortC pullhigh resister Islp Sleep current (WDT disable) Sleep current (WDT enable) Islp VDD=5V VDD=5V, IOL=20mA VDD=5V, IOL=5mA VDD=5V, IOH= -20mA VDD=5V, IOH= -5mA VDD=5V VDD=5V VDD=5V VDD2.3 ~ 6.3 V VDD2.3 V VDD3.0 V VDD4.0 V VDD5.0 V VDD6.3 V Sleep current Islp-L (LCD on at CAP MODE),no load Sleep current (LCD on at RES MODE),no load Vpr Power Edge-detector Reset Voltage Vdd=5.0 V Vdd=3.0 v Vdd=5.0 V Vdd=3.0 v
A 1.3 V
1.1
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.20 2007/11
VER 1.0
MDT11P0122
Sym Description The basic WDT time-out cycle time Twdt Condition VDD2.3 V VDD3.0 V VDD4.0 V VDD5.0 V VDD6.3 V TFLT /MCLR filter Vref Input reference voltage Comparator Response time V-=VDD/4, V+=V- 0.2v V-=VDD/2, V+=V- 0.2v V-=VDD3/4, V+=V- 0.2v V-=VDD-0.8,V+=V 0.2v Lrc Internal LCD RC VDD=5v VDD=5v Ires Internal LCD resister current between vlcd pin and VDD VDD=3v 1/3bias 1/2bias 1/3bias 1/2bias 15 VDD5.0 V VDD=2.5v ~6.3v VDD=5.0v , V- = Vref V+ = (PA0~PA3) Min Typ 26.4 23.6 20.1 20.4 16.4 600 VDD Max Unit mS mS mS mS mS nS V S S S S 35 kHz
---
8 8 8 8 10 30 0.1 4
A
10.
Equivalent Circuit Port A PA0,PA2
D I/O C o n tro l P u ll-H ig h c o n tro l P o r t I/O P in D W r ite D a ta O /P L a tc h G QB Q I/O C o n tro l L a tc h CK QB P u ll-h ig h 50K
In p u t R e s is to r
D a ta B u s D QB D a ta I/P L a tc h G
0 T T L in p u t le v e l S + c o m p a ra to r le v e l
R ead
1
VREF
C o m p a rto r C o n tro l
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.21 2007/11
VER 1.0
MDT11P0122
PA1,PA3
D Q P ull_H i 50K
I/O C ontrol
CK
I/O C ontrol L atch
QB
Pull_H i C ontrol
P ort I/O Pin D
W rite G
D ata O /P L atch
QB
Input R esistor D ata B us QB D com parator enable
R ead
D ata I/P L atch
G
T T L Input L evel 3 2 3/4 V D D 1/2 V D D 1/4 V D D
V ref
S0 S1 C M P R S0 C M P R S1
1 0
PA4,PA5
D
Q
P u ll_ H i 5 0 k
I/O C o n tro l
I/O C o n tro l L a tc h
C K QB
P u ll_ H i C o n tro l
P o rt I/O P in
D
W rite G
D a ta O /P L a tc h
QB In p u t R e s isto r
D a ta B u s
T T L in p u t le v e l
R ead
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.22 2007/11
VER 1.0
MDT11P0122
Port B
D
Q
I/O Control
CK
I/O Control Latch
QB
Pull_Hi 50K
Pull_Hi Control
Port I/O Pin D
Write G
Data O/P Latch
QB
Data Bus QB D
Read
Data I/P Latch
G
Input Resistor TTL Input Level
Port C
D
Q
I/O Control
I/O Control Latch
CK QB
Pull_Hi 100k
Pull_Hi Control
Port I/O Pin
D
Write G
Data O/P Latch
QB Input Resistor
Data Bus
SMI input level
Read
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.23 2007/11
VER 1.0
MDT11P0122
Port D PD0~PD3
LCD SEG
LCD SEG e n a b le
D
I/O C o n tro l
CK
I/O C o n tro l L a tc h
QB
P o rt I /O P in D
W rite G
D a ta O /P L a tc h
QB
D a ta B u s QB D
R ead
D a ta I/P L a tc h
G
S M I In p u t L e v e l
In p u t R e s is to r
PD5~PD7
LCD COM
Port I/O Pin
LCDPFS(N)
Data Bus QB D
Read
Data I/P Latch
G
SMI Input Level
Input Resistor
VDD
CPIO D
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.24 2007/11
VER 1.0
MDT11P0122
Port EFG
LCD SEG
LCDPFS(N)
Port input/ LCD output Pin
Input Resistor
Data Bus
SMI Input Level
Read
VDD
CPIO
MCLRB PIN
R1K
MCLRB Schmitt Trigger
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.25 2007/11
VER 1.0
MDT11P0122
11. External Capacitor Selection For Crystal Oscillator
Osc. Type HF Resonator Freq. 20 MHz 10 MHz 4 MHz 10 MHz XT 4 MHz 1 MHz 1 MHz LF 455 K 32 K C1 5 pF ~10 pF 10 pF ~50 pF 10 pF ~50 pF 10 pF ~30 pF 10 pF ~50 pF 10 pF ~30 pF 3 pF ~5 pF 10 pF ~30 pF 10 pF ~20 pF C2 10 pF ~30 pF 20 pF ~100 pF 20 pF ~100 pF 10 pF ~50 pF 20 pF ~100 pF 20 pF ~50 pF 3 pF ~5 pF 20 pF ~50 pF 15 pF ~30 pF
MDT11P0122
OSC1 OSC2
C1
C2
To increase the stability of oscillator and the ability of anti-noise, the above values of the external capacitor are for reference only, but the higher capacitance also increases the start-up time.
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.26 2007/11
VER 1.0
MDT11P0122
12. Timer1 comapre mode
CCP1CTL Enable CCP1
Input COMPARATOR
1/2
Output
PC2
TMR1
Clear TMR1L
PC2
PC2 OUTPUT ENABLE
13. Lcd application
(1) LCD voltage generation at capacitance mode
Input Output
Default
13. LCD APPLICATION
(1) LCD voltage generation at CAP mode
1/2 BIAS CAP MODE VLCD3 VLCD2 Vlcd Vlcd 3 Vlcd 2 C1 C2 0 VDD 1/2VDD VSS
*0.1u
Vdd Vdd
*0.1u
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.27 2007/11
VER 1.0
MDT11P0122
1/3 BIAS CAP MODE VLCD3 VDD VLCD2 Vlcd Vlcd 3 Vlcd 2 C1 C2 0 VSS 3/2VDD VDD 1/2VDD
*0.1u
*0.1u *0.1u
Vdd
*These value are adjusted to the application by designer
(2) LCD voltage generation at resister mode
RES MODE
1/3 BIAS VLCD 2/3VLCD 1/3VLCD
1/2 BIAS VLCD 1/2VLCD VSS
Vlcd
Vlcd 3
Vlcd 2
C1
C2 VSS
Vdd
* Designer can adjust vlcd resister to change lcd voltage at resister mode.
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.28 2007/11
VER 1.0
MDT11P0122
(3) LCD Interrupt ( in 1/3 bias, 1/4 duty )
COM0
VLCD3 VDD VLCD2 0 VLCD3 VDD VLCD2 0
COM1
COM2
VLCD3 VDD VLCD2 0
COM3
VLCD3 VDD VLCD2 0
LCDINT 1 Frame 1 Frame 1 Frame 1 Frame
This interrupt can be used to write next frame data
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.29 2007/11
VER 1.0

▲Up To Search▲

Price & Availability of MDT11P0122

	To Download MDT11P0122 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .